1. Field of the Invention
The present invention relates to a circuit for sensing a memory having a plurality of threshold voltages and a method therefor, and in particular to an improved circuit for sensing a memory having a plurality of threshold voltages and a method therefor which are capable of accurately sensing a memory by reducing a distance between a threshold voltage distribution width and a distribution width of a memory having a plurality of threshold voltages and being well adapted to reading a data from a memory or sensing the same at a lower voltage.
2. Description of the Background Art
In a programmable memory which is programmed or erased to have a plurality of threshold voltage levels, each threshold voltage level has a predetermined distribution by a process characteristic variation, an operational accuracy of a programming circuit, a temperature variation, etc. Therefore, reducing the width of the distribution and increasing the distance between the distributions are important factors for enhancing the reliability of a sensing operation.
As shown in FIG. 1, the known circuit for sensing a memory having a plurality of threshold voltages includes a first PMOS transistor PM1 the source of which receives a supply power voltage VDD the gate of which is connected with the drain of the same and the memory, and comparators COM1, COM2, and COM3 having first input terminals commonly connected with the drain of the first PMOS transistor PM1 and second input terminals receiving first, second and third reference voltages Vref1, Vref2 and Vref3, respectively.
In the thusly constituted circuit, a plurality of reference voltages or reference voltages are used for sensing the states corresponding to a predetermined threshold voltage distribution, and the threshold voltage distribution .DELTA.Vth formed due to various external causes such as a process characteristic variation, an accuracy of a reference voltage, a temperature variation, etc. is directly used. Therefore, when the number of threshold voltages is increased and the voltage applied to the sensing circuit becomes a low level voltage, it is impossible to perform a sensing operation.
In order to overcome the above problems, as shown in FIG. 2, a circuit which is capable of sensing a memory having a plurality of threshold voltages is disclosed, which includes a current mirror 20 one terminal of which is connected with a memory 10, a voltage-matched circuit 30 an output terminal of which is connected with another terminal of the current mirror 20, a comparator 40 one terminal of which is commonly connected with the current mirror 20 and the voltage-matched circuit 30 and another terminal of which receives a reference voltage from a reference voltage distributor 60 for thereby comparing the thusly received two inputs, and a decoding logic circuit 50 for decoding an output signal from the comparator 40.
Here, the current mirror 20 includes a first PMOS transistor PM21 and a second PMOS transistor PM22 wherein the sources of which are connected with each other and receive the supply voltage VDD and the gates of which are connected with each other and then connected with the memory 10, and the drain of the first PMOS transistor PM21 is connected with the voltage-matched circuit 30.
As shown in FIG. 3, the voltage-matched circuit 30 includes a first NMOS transistor NM31 the drain of which receives a reference current voltage IREF, the source of which is connected with a ground voltage VSS, the gate and drain of which are commonly connected, NMOS transistors NM32 through NM35 the gates of which are commonly connected with the gate of the first NMOS transistor NM31 and the drains of which are connected with a ground voltage VSS, an NMOS transistor NM36 the gate of which is connected with the voltage VOUT, an NMOS transistor NM37 the gate of which is connected with the source of the NMOS transistor NM36 and the drain is connected with the voltage VOUT, and an NMOS transistor NM38 the gate of which is connected with the source of the NMOS transistor NM37, and the drain of which is commonly connected with the drains of the NMOS transistors NM36 and NM37 and the voltage VOUT.
The operation of the known circuit for sensing a memory having a plurality of threshold voltages will be explained with reference to the accompanying drawings.
The quantization threshold voltage is generated by adapting an uncertainty of the threshold voltage of the memory and the threshold voltage distribution based on a quantization technique, so that a reading and writing operation is implemented based on the thusly generated voltage value.
As shown in FIG. 4, the voltage quantization technique is implemented by matching one-to-one a plurality of voltage distributions having a predetermined width and distance with the quantized voltage.
FIG. 4C illustrates a step shape function between an input terminal current and an output terminal current of a circuit which perform a voltage quantization function.
Here, assuming that the hatched region of the current distribution corresponds with the cell current corresponding with the threshold voltage distribution of the memory, the above current distribution is biased in the region in which each signal resistance value is small. If the resistance value is very small, an one-to-one mapping operation is performed with respect to the quantized voltages V0, V1 and V3.
Therefore, it is possible to obtain an output signal having a predetermined distribution irrespective of the original threshold voltage distribution using a circuit having the above-described curve characteristic.
When the inclination of each step is increased, the distribution of the threshold voltage which is mapped is narrowed.
In order to implement a mapping current voltage having the characteristic of a step shape function, a current flow is blocked at a predetermined voltage level interval, and when the voltage levels at both ends exceed a predetermined level, the current flow is repeatedly performed.
As shown in FIG. 3, the voltage-matched circuit 30 is a circuit for quantizing a voltage distribution of a memory having four threshold voltage distributions and includes one current mirror and three cascode current sources. Here, it is assumed that the sizes of all transistors are identical.
An output voltage VO that the second NMOS transistor NM32 forming a current mirror outputs is a saturated voltage Vsat, and the voltage by which the current paths of the NMOS transistors NM33 and NM36 forming a first cascode current power is a threshold voltage of a sixth NMOS transistor NM36, and the voltage V1 by which the first cascode current power is saturated is the value which is obtained by adding the saturated voltage Vsat to the reference voltage Vref. The voltage V2 by which the second cascode current power is saturated is a value which is obtained by adding the saturated voltage 2Vsat (doubled) to the reference voltage Vref, and the voltage V3 by which the third cascode current power is saturated is a value which is obtained by adding the saturated voltage 3Vsat (tripled) to the reference voltage Vref.
Therefore, as shown in FIG. 4C, in the graph of the output current with respect to the mapped threshold voltage, a step shape is obtained based on a voltage quantizing function in which the current is sharply increased.
Here, since it is possible to form a predetermined step shape by controlling the reference current Iref, the reference voltage Vref and the sizes of each transistor, the distance between the voltage distributions and the distribution of the threshold voltage (current) are controlled.
The output signal having a threshold voltage distribution of a memory determined by the characteristic of a step shape function as illustrated in FIG. 4 is inputted into the comparator 40 and is compared with reference voltages Vref1, Vref2 and Vref3 outputted from the reference voltage distributor, so that the states of the output signals become recognizable.
Here, since the reference voltages Vref1, Vref2 and Vref3 are determined by the characteristic of the threshold voltage mapped irrespective of the threshold voltage distribution characteristic of the cell, it is possible to implement a desired characteristic of the voltages.
Here, each reference voltage is determined based on the following equations . EQU Vref1=(VO+V1)/2 EQU Vref2=(V1+V2)/2 EQU Vref3=(V2+V3)/2
Assuming that there are an n-number of states, an (n-1) number of reference voltages is needed. The output signal values X1, X2 and X3 outputted from the comparator 40 are outputted as digital values MSB and LSB through the decoding logic circuit 50.
As described above, in the known circuit for sensing a memory having a plurality of threshold voltages, when the states of the memory are increased, the distance between the distributions is decreased and the width of the distribution is widened, so that the reliability of the sensing operation is decreased, and the number of states stored in one memory is limited.
The above-described voltage mapping current power has four states. If the states are increased or decreased, the number of branches may be increased or decreased.
However, in the known sensing circuit using a voltage-matched circuit, since the distance between the distributions of the threshold voltages is limited by the threshold voltage of each transistor which is a minimum value of the reference voltage, it is difficult to sense the distributions and distances of more than four threshold voltages at an external voltage of 3.3V.